1. Field of the Invention
The present invention relates to the field of memories and more specifically of ROMs.
2. Discussion of the Related Art
Conventionally, in a ROM, storage elements or memory points are arranged at the intersection of rows and columns, each memory point being likely to memorize a binary state, that is, a 0 or a 1. Thus, each memory point is a single-bit point.
To reduce the size of memories, it has been provided that each memory point, instead of being able to be in one or the other of two states, is likely to provide a richer information, characteristic for example of one or the other of three or four states. Preferably, for memory management reasons, it would be preferred for each memory point to be able to memorize an integral number of bits, that is, a number of data equal to an integral power of 2. Each memory point would for example correspond to a transistor, the conduction level of which would be greater or smaller when controlled to be in the on state. For this purpose, it may be envisaged to provide, at the level of each memory point, transistors of larger or smaller size, or again to provide transistors with a floating gate, the gate of which is more or less precharged. However, none of these solutions has been crowned with industrial success in standard CMOS technology, most likely because all these solutions imply relatively complex technological operations and require comparing a voltage or current level with several distinct thresholds. This operation is always relatively complex and risks suffering from a lack of reliability if the component characteristics drift.
Thus, an object of the present invention is to enable storage in a simple memory point of several data, that is, an information of several bits, or multibit information.
Another object of the present invention is to provide an array of such memory points in which the memory points are all identical.
Another object of the present invention is to provide such a memory point array in which the read operations are binary and reliable.
Another object of the present invention is to provide such a memory point array which is particularly easy to form and which takes up little room on an integrated circuit.
To achieve these objects, the present invention provides a ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N greater than =2. Each column includes 2N conductive lines; each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2N connections from among the set of 22N possible connections; and each of N read means is provided to apply a precharge voltage to a chosen group of 2N first lines, connect the 2N other lines to a reference voltage, select a memory point, read the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.
According to an embodiment of the present invention, each switch is a MOS transistor, two adjacent transistors of a same column having a common source/drain region.
According to an embodiment of the present invention, the gates of the MOS transistors of a same row are interconnected.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.